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Vorlage:Importartikel/Wartung-2019-09

Vorlage:Short description Vorlage:Use dmy dates Vorlage:Infobox company Vorlage:Chinese

HiSilicon (chinesisch 海思, Pinyin Hǎisī) is a Chinese fabless semiconductor company based in Shenzhen, Guangdong and fully owned by Huawei.

HiSilicon purchases licenses for CPU designs from ARM Holdings, including the ARM Cortex-A9 MPCore, ARM Cortex-M3, ARM Cortex-A7 MPCore, ARM Cortex-A15 MPCore,[1][2] ARM Cortex-A53, ARM Cortex-A57 and also for their Mali graphics cores.[3][4] HiSilicon has also purchased licenses from Vivante Corporation for their GC4000 graphics core.

HiSilicon is reputed to be the largest domestic designer of integrated circuits in China.[5]

Smartphone Application Processors[Bearbeiten | Quelltext bearbeiten]

HiSilicon develops SoCs based on ARM architecture. Though not exclusive, these SoCs see preliminary use in handheld and tablet devices of its parent company Huawei.

K3V2[Bearbeiten | Quelltext bearbeiten]

The first well known product of HiSilicon is the K3V2 used in Huawei Ascend D Quad XL (U9510) smartphones[6] and Huawei MediaPad 10 FHD7 tablets.[7] This chipset is based on the ARM Cortex-A9 MPCore fabbed at 40 nm and uses a 16 core Vivante GC4000 GPU.[8] The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
K3V2 (Hi3620) 40 nm ARMv7 Cortex-A9 L1: 32 KB instruction + 32 KB data, L2: 1 MB 4 1.4 Vivante GC4000 240 MHz

(15.3GFlops)

LPDDR2 64-bit dual-channel 7.2 (up to 8.5) — — — — Q1 2012 Vorlage:Collapsible list

K3V2E[Bearbeiten | Quelltext bearbeiten]

This is a revised version of K3V2 SoC with improved support of Intel baseband. The SoC supports LPDDR2-1066, but actual products are found with LPDDR-900 instead for lower power consumption.

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
K3V2E 40 nm ARMv7 Cortex-A9 L1: 32 KB instruction + 32 KB data, L2: 1 MB 4 1.5 Vivante GC4000 240 MHz

(15.3GFlops)

LPDDR2 64-bit dual-channel 7.2 (up to 8.5) — — — — 2013 Vorlage:Collapsible list

Kirin 620[Bearbeiten | Quelltext bearbeiten]

• supports - USB 2.0 / 13 MP / 1080p video encode

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 620 28 nm ARMv8-A Cortex-A53 8 1.2 Mali-450 MP4 533 MHz (32GFlops) LPDDR3 ( MHz) 32-bit single-channel 6.4 — Dual SIM LTE Cat.4 (150 Mbit/s) 802.11 b/g/n (Wifi Direct & Hotspot) Not Supporting DLNA / Miracast Bluetooth v4.0, A2DP, EDR, LE Q1 2015 Vorlage:Collapsible list

Kirin 650, 655, 658, 659[Bearbeiten | Quelltext bearbeiten]

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 650 16 nm FinFET+ ARMv8-A Cortex-A53
Cortex-A53 		4+4 2.0 (4xA53) 1.7 (4xA53) Mali-T830 MP2 900 MHz

(40.8GFlops)

LPDDR3 (933 MHz) 64-bit dual-channel (2x32bit)[9] A-GPS, GLONASS Dual SIM LTE Cat.6 (300 Mbit/s) 802.11 b/g/n Bluetooth v4.1 Q2 2016 Vorlage:Collapsible list
Kirin 655 2.12 (4xA53) 1.7 (4xA53) Q4 2016 Vorlage:Collapsible list
Kirin 658 2.35 (4xA53) 1.7 (4xA53) 802.11 b/g/n/ac Q2 2017 Vorlage:Collapsible list
Kirin 659 2.36 (4xA53) 1.7 (4xA53) 802.11 b/g/n Bluetooth v4.2 Q3 2017 Vorlage:Collapsible list

Kirin 710[Bearbeiten | Quelltext bearbeiten]

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 710 12 nm FinFET ARMv8-A Cortex-A73
Cortex-A53 		4+4 2.2 (4xA73) 1.7 (4xA53) Mali-G51 MP4 1000 MHz ??? A-GPS, GLONASS Dual SIM LTE Cat.12 (600 Mbit/s) 802.11 b/g/n Bluetooth v4.2 Q3 2018 Vorlage:Collapsible list

Kirin 810[Bearbeiten | Quelltext bearbeiten]

  • DaVinci NPU based on Tensor Arithmetic Unit
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 810 7 nm FinFET ARMv8.2-A Cortex-A76
Cortex-A55
DynamIQ 		2+6 2.2 (2xA76) 1.9 (6xA55) Mali-G52 MP6 820 MHz LPDDR4X ? ? A-GPS, GLONASS, BDS Dual SIM LTE Cat.12 (600 Mbit/s) 802.11 b/g/n/ac Bluetooth v5.0 Q2 2019
  • Huawei Nova 5
  • Huawei Honor 9x
  • Huawei Honor 9x Pro

Kirin 910 and 910T[Bearbeiten | Quelltext bearbeiten]

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 910 28 nm HPM ARMv7 Cortex-A9 4 1.6 Mali-450 MP4 533 MHz

(32GFlops)

LPDDR3 32-bit single-channel 6.4 — LTE Cat.4 — — H1 2014 Vorlage:Collapsible list
Kirin 910T 1.8 700 MHz

(41.8GFlops)

— — — H1 2014 Vorlage:Collapsible list

Kirin 920, 925 and 928[Bearbeiten | Quelltext bearbeiten]

• The Kirin 920 SoC also contains an image processor that supports up to 32 megapixel

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 920 28 nm HPM ARMv7 Cortex-A15
Cortex-A7
big.LITTLE		 4+4 1.7 (A15)
1.3 (A7) 		Mali-T628 MP4 600 MHz

(76.8GFlops)

LPDDR3 (1600 MHz) 64-bit dual-channel 12.8 — LTE Cat.6 (300 Mbit/s) — — H2 2014 Vorlage:Collapsible list
Kirin 925 1.8 (A15)
1.3 (A7) 		— — — Q3 2014 Vorlage:Collapsible list
Kirin 928 2.0 (A15)
1.3 (A7) 		— — — — Vorlage:Collapsible list

Kirin 930 and 935[Bearbeiten | Quelltext bearbeiten]

• supports - SD 3.0 (UHS-I) / eMMC 4.51 / Dual-band a/b/g/n Wi-Fi / Bluetooth 4.0 Low Energy / USB 2.0 / 32 MP ISP / 1080p video encode

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 930 28 nm HPC ARMv8-A Cortex-A53
Cortex-A53 		4+4 2.0 (A53)
1.5 (A53) 		Mali-T628 MP4 600 MHz

(76.8GFlops)

LPDDR3 (1600 MHz) 64-bit(2x32-bit) Dual-channel 12.8 GB/s — Dual SIM LTE Cat.6 (DL:300 Mbit/s UP:50 Mbit/s) — — Q1 2015 Vorlage:Collapsible list
Kirin 935 2.2 (A53)
1.5 (A53) 		680 MHz

(87GFlops)

— — — Q1 2015 Vorlage:Collapsible list

Kirin 950 and 955[Bearbeiten | Quelltext bearbeiten]

• supports - SD 4.1 (UHS-II) / UFS 2.0 / eMMC 5.1 / MU-MIMO 802.11ac Wi-Fi / Bluetooth 4.2 Smart / USB 3.0 / NFS / Dual ISP (42 MP) / Native 10-bit 4K video encode / i5 coprocessor / Tensilica HiFi 4 DSP

Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 950 TSMC 16 nm FinFET+[10] ARMv8-A Cortex-A72
Cortex-A53
big.LITTLE 		4+4 2.3 (A72)
1.8 (A53) 		Mali-T880 MP4 900 MHz

(122.4GFlops)

LPDDR4 64-bit(2x32-bit) Dual-channel 25.6 — Dual SIM LTE Cat.6 — — Q4 2015 Vorlage:Collapsible list
Kirin 955[11] 2.5 (A72)
1.8 (A53) 		LPDDR3 (3 GB) LPDDR4 (4 GB) — — — Q2 2016 Vorlage:Collapsible list

Kirin 960[Bearbeiten | Quelltext bearbeiten]

  • Interconnect: ARM CCI-550, Storage: UFS 2.1, eMMC 5.1, Sensor Hub: i6
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 960[12] TSMC 16 nm FFC ARMv8-A Cortex-A73
Cortex-A53
big.LITTLE 		4+4 2.36 (A73)
1.84 (A53) 		Mali-G71 MP8 1037 MHz

(282GFlops)

LPDDR4-1600 64-bit(2x32-bit) Dual-channel 28.8 — Dual SIM LTE Cat.12 LTE 4x CA, 4x4 MIMO — — Q4 2016 Vorlage:Collapsible list

Kirin 970[Bearbeiten | Quelltext bearbeiten]

  • Interconnect: ARM CCI-550, Storage: UFS 2.1, Sensor Hub: i7
  • Cadence Tensilica Vision P6 DSP.[13]
  • NPU made in collaboration with Cambricon Technologies. 1.92T FP16 OPS.[14]
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 970 TSMC 10 nm FinFET+ ARMv8-A Cortex-A73
Cortex-A53
big.LITTLE 		4+4 2.36 (A73)
1.84 (A53) 		Mali-G72 MP12 746 MHz

(330 GFlops)

LPDDR4X-1866 64-bit(4x16-bit) Quad-channel 29.8 Galileo Dual SIM LTE Cat.18 LTE 5x CA, No 4x4 MIMO — — Q4 2017 Vorlage:Collapsible list

Kirin 980[Bearbeiten | Quelltext bearbeiten]

It is HiSilicon's first SoC based on 7 nm FinFet technology.

  • Interconnect: ARM Mali G76-MP10, Storage: UFS 2.1, Sensor Hub: i8
  • Dual NPU made in collaboration with Cambricon Technologies.
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 980 TSMC 7 nm FinFET ARMv8.2-A Cortex-A76
Cortex-A55
DynamIQ 		(2+2)+4 2.6 (A76 H)
1.92 (A76 L)
1.8 (A55) 		Mali-G76 MP10 720 MHz

(489.6 GFlops)[15]

LPDDR4X-2133 64-bit(4x16-bit) Quad-channel 34.1 Galileo Dual SIM LTE Cat.21 LTE 5x CA, No 4x4 MIMO — — Q4 2018
  • Huawei Mate 20
  • Huawei Mate 20 Pro
  • Huawei Mate 20 RS Porsche Design
  • Huawei Mate 20 X
  • Honor Magic 2
  • Honor View 20/V20
  • Honor 20
  • Honor 20 Pro
  • Huawei P30
  • Huawei P30 Pro
  • Huawei Nova 5 Pro

Kirin 990 4G & 990 5G[Bearbeiten | Quelltext bearbeiten]

Kirin 990 5G is HiSilicon's first SoC based on N7+ nm FinFet technology.

  • Interconnect: ARM Mali G76-MP16
  • Da Vinci NPU
    • Kirin 990 4G: 1 big Da Vinci core + 1 tiny Da Vinci core
    • Kirin 990 5G: 2 big Da Vinci core + 1 tiny Da Vinci core
Model Number Fab CPU GPU Memory Technology Nav Wireless Sampling Availability Utilizing Devices
ISA Microarchitecture Cores Frq (GHz) Microarchitecture Frq (MHz) Type Bus width (bit) Bandwidth (GB/s) Cellular WLAN PAN
Kirin 990 4G TSMC 7nm FinFET (DUV) ARMv8.2-A Cortex-A76
Cortex-A55
DynamIQ 		(2+2)+4 2.86 (A76 H)
2.36 (A76 L)
1.95 (A55) 		Mali-G76 MP16 700 MHz
(761.6 GFlops) 		LPDDR4X-2133 64-bit(4x16-bit) Quad-channel 34.1 Galileo Balong 765 — — Q4 2019 Huawei Mate 30 Pro
Kirin 990 5G TSMC 7nm+ FinFET (EUV) 2.86 (A76 H)
2.09 (A76 L)
1.95 (A55) 		Balong 5000 (Sub-6-GHz only) — —


Smartphone modems[Bearbeiten | Quelltext bearbeiten]

HiSilicon develops smartphone modems which although not exclusively, these SoCs see preliminary use in handheld and tablet devices of its parent company Huawei.

Balong 700[Bearbeiten | Quelltext bearbeiten]

The Balong 700 supports LTE TDD/FDD.[16] Its specs:

  • 3GPP R8 protocol
  • LTE TDD and FDD
  • 4x2/2x2 SU-MIMO

Balong 710[Bearbeiten | Quelltext bearbeiten]

At MWC 2012 HiSilicon released the Balong 710.[17] It is a multi-mode chipset supporting 3GPP Release 9 and LTE Category 4 at GTI (Global TD-LTE Initiative). The Balong 710 was designed to be used with the K3V2 SoC. Its specs:

  • LTE FDD mode : 150 Mbit/s downlink and 50 Mbit/s uplink.
  • TD-LTE mode: up to 112 Mbit/s downlink and up to 30 Mbit/s uplink.
  • WCDMA Dual Carrier with MIMO: 84Mbit/s downlink and 23Mbit/s uplink.

Balong 720[Bearbeiten | Quelltext bearbeiten]

The Balong 720 supports LTE Cat6 with 300 Mbit/s peak download rate.[16] Its specs:

  • TSMC 28nm HPM process
  • TD-LTE Cat.6 standard
  • Dual-carrier aggregation for the 40 MHz bandwidth
  • 5-mode LTE Cat6 Modem

Balong 750[Bearbeiten | Quelltext bearbeiten]

The Balong 750 supports LTE Cat 12/13, and it is first to support 4CC CA and 3.5GHz.[16] Its specs:

  • LTE Cat.12 and Cat.13 UL network standards
  • 2CC (dual-carrier) data aggregation
  • 4x4 multiple-input multiple-output (MIMO)
  • TSMC 16nm FinFET+ process

Balong 765[Bearbeiten | Quelltext bearbeiten]

The Balong 765 supports 8×8 MIMO technology, LTE Cat.19 with downlink data-rate up to 1.6 Gbit/s in FDD network and up to 1.16 Gbit/s in the TD-LTE network.[18] Its specs:

  • 3GPP Rel.14
  • LTE Cat.19 Peak data rate up to 1.6 Gbit/s
  • 4CC CA + 4×4 MIMO/2CC CA + 8×8 MIMO
  • DL 256QAM
  • C-V2X

Balong 5G01[Bearbeiten | Quelltext bearbeiten]

The Balong 5G01 supports the 3GPP standard for 5G with downlink speeds of up to 2.3 Gbit/s. It supports 5G across all frequency bands including sub-6GHz and millimeter wave (mmWave).[16] Its specs:

  • 3GPP Release 15
  • Peak data rate up to 2.3 Gbit/s
  • Sub 6GHz and mmWave
  • NSA/SA
  • DL 256QAM

Balong 5000[Bearbeiten | Quelltext bearbeiten]

The Balong 5000 supports supports 2G, 3G, 4G, and 5G.[19] Its specs:

  • 2G/3G/4G/5G Multi Mode
  • Fully compliant with 3GPP Release 15
  • Sub-6GHz: 100MHz x 2CC CA
  • Sub-6GHz：Downlink up to 4.6 Gbit/s, Uplink up to 2.5 Gbit/s
  • mmWave：Downlink up to 6.5 Gbit/s, Uplink up to 3.5 Gbit/s
  • NR+LTE：Downlink up to 7.5 Gbit/s
  • FDD & TDD Spectrum Access
  • SA & NSA Fusion Network Architecture
  • Supports 3GPP R14 V2X
  • 3GB LPDDR4X[20]

Server processors[Bearbeiten | Quelltext bearbeiten]

HiSilicon develops server processor SoCs based on ARM architecture.

Hi1610[Bearbeiten | Quelltext bearbeiten]

The Hi1610 is HiSilicon's first generation server processor announced in 2015. It features:

  • 16x ARM Cortex-A57 at up to 2.1 GHz[21]
  • 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 16MB CCN L3
  • TSMC 16nm
  • 2x DDR4-1866
  • 16 PCIe 3.0

Hi1612[Bearbeiten | Quelltext bearbeiten]

The Hi1612 is HiSilicon's second generation server processor launched in 2016. It features:

  • 32x ARM Cortex-A57 at up to 2.1 GHz[21]
  • 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 32MB CCN L3
  • TSMC 16nm
  • 4x DDR4-2133
  • 16 PCIe 3.0

Kunpeng 916 (formally Hi1616)[Bearbeiten | Quelltext bearbeiten]

The Kunpeng 916 (formally known as Hi1616) is HiSilicon's third generation server processor launched in 2017. The Kunpeng 916 is utilized in Huawei's TaiShan 2280 Balanced Server, TaiShan 5280 Storage Server, TaiShan XR320 High-Density Server Node and TaiShan X6000 High-Density Server. [22][23][24][25] It features:

  • 32x Arm Cortex-A72 at up to 2.4 GHz[21]
  • 48 KB L1-I, 32 KB L1-D, 1MB L2/4 cores and 32MB CCN L3
  • TSMC 16nm
  • 4x DDR4-2400
  • 2-way Symmetric multiprocessing (SMP), Each socket has 2x ports with 96 Gbit/s per port (total of 192 Gbit/s per each socket interconnects)
  • 46 PCIe 3.0 and 8x 10 GbE
  • 85 W

Kunpeng 920 (formally Hi1620)[Bearbeiten | Quelltext bearbeiten]

The Kunpeng 920 (formally known as Hi1620) is HiSilicon's fourth generation server processor announced in 2018, launched in 2019. Huawei claim the Kunpeng 920 CPU scores more than an estimated 930 on SPECint®_rate_base2006.[26] The Kunpeng 920 is utilized in Huawei's TaiShan 2280 V2 Balanced Server, TaiShan 5280 V2 Storage Server and TaiShan XA320 V2 High-Density Server Node.[27][28][29] It features:

  • 32 to 64x custom TaiShan v110 cores at up to 2.6 GHz.[30]
  • The TaiShan v110 core is a 4-way out-of-order superscalar that implements the ARMv8.2-A ISA. Huawei reports the core supports almost all the ARMv8.4-A ISA features with a few exceptions, including dot product and the FP16 FML extension.[30]
  • The TaiShan v110 cores are likely a new core not based off ARM designs [31]
  • 3x Simple ALUs , 1x Complex MDU, 2x BRUs (sharing ports with ALU2/3), 2x FSUs (ASIMD FPU), 2x LSUs[31]
  • 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1MB L3/core Shared.
  • TSMC 7nm HPC
  • 8x DDR4-3200
  • 2-way and 4-way Symmetric multiprocessing (SMP). Each socket has 3x Hydra ports with 240 Gbit/s per port (total of 720 Gbit/s per each socket interconnects)
  • 40 PCIe 4.0 with CCIX support, , 4 USB 3.0, 2x SATA 3.0, x8 SAS 3.0 and 2 x 100 GbE
  • 100 to 200 W
  • Compression engine (GZIP, LZS, LZ4) capable of up to 40 Gib/s compress and 100 Gbit/s decompress
  • Crypto offload engine (for AES, DES, 3DES, SHA1/2, etc..) capable of throughputs up to 100 Gbit/s

Kunpeng 930 (formally Hi1630)[Bearbeiten | Quelltext bearbeiten]

The Kunpeng 930 (formally known as Hi1630) is HiSilicon's fifth-generation server processor announced in 2019 and scheduled for launch in 2021. It features:

  • TBD custom cores with higher frequencies, support for simultaneous multithreading (SMT) and Arm’s Scalable Vector Extension (SVE).[30]
  • 64 KB L1-I, 64 KB L1-D, 512 KB Private L2 and 1MB L3/core Shared
  • TSMC 7nm?
  • 8x DDR5

Kunpeng 950[Bearbeiten | Quelltext bearbeiten]

The Kunpeng 950 is HiSilicon's sixth-generation server processor announced in 2019 and scheduled for launch in 2023

AI Acceleration[Bearbeiten | Quelltext bearbeiten]

HiSilicon also develops AI Acceleration chips.

Da Vinci architecture[Bearbeiten | Quelltext bearbeiten]

Each Da Vinci Max AI Core features a 3D Cube Tensor Computing Engine (4096 FP16 MACs + 8192 INT8 MACs), Vector unit (2048bit INT8/FP16/FP32) and scalar unit. It includes a new AI framework called "MindSpore", a platform-as-a-service product called ModelArts, and a lower-level library called Compute Architecture for Neural Networks (CANN).[32]

Ascend 310[Bearbeiten | Quelltext bearbeiten]

The Ascend 310 is an AI inference SoC, it was codenamed Ascend-Mini. The Ascend 310 is capable of 16 TOPS@INT8 and 8 TOPS@FP16.[33] The Ascend 310 features:

  • 2x Da Vinci Max AI cores[32]
  • 8x ARM Cortex-A55 CPU cores
  • 8MB On-chip buffer
  • 16 Channel Video Decode - H.264/H.265
  • 1 Channel Video Encode - H.264/H.265
  • TSMC 12nm FFC Process
  • 8W

Ascend 910[Bearbeiten | Quelltext bearbeiten]

The Ascend 910 is an AI training SoC, it was codenamed Ascend-Max. which delivers 256 TFLOPS@FP16 and 512 TOPS@INT8. The Ascend 910 features:

  • 32x Da Vinci Max AI cores arranged in 4 clusters[32]
  • 1024-bit NoC Mesh @ 2GHz, with 128 GBps bandwidth Read/Write per core
  • 3x 240Gbps HCCS ports for Numa connctions
  • 2x 100Gbps RoCE interfaces for networking
  • 4x HBM2E, 1.2 TBps bandwidth
  • 3D-SRAM stacked below AI SoC die
  • 1228mm2 Total die size (456mm2 Virtuvian AI SoC, 168mm2 Nimbus V3 IO Die, 4x96mm2 HBM2E, 2x110mm2 Dummy Die)
  • 32MB On-chip buffer
  • 128 Channel Video Decode - H.264/H.265
  • TSMC 7+ nm EUV (N7+) Process
  • 350W

The Ascend 910 Cluster has 1024-2048 Ascend 910 chips to reach 256-512 petaFLOPS@FP16. The Ascend 910 and Ascend Cluster will be available in Q2 2019.[34]

Similar platforms[Bearbeiten | Quelltext bearbeiten]

The Kirin processors compete with products from several other companies, including:

References[Bearbeiten | Quelltext bearbeiten]

Vorlage:Reflist

External links[Bearbeiten | Quelltext bearbeiten]

Portal: Companies – Übersicht zu Wikipedia-Inhalten zum Thema Companies

Vorlage:Huawei Vorlage:Electronics industry in China Vorlage:Application ARM-based chips

Category:Fabless semiconductor companies Category:ARM architecture Category:Semiconductor companies of China Category:Companies based in Shenzhen Category:Chinese brands Category:Huawei Category:Chinese companies established in 2004

  1. ↑ HiSilicon Licenses ARM Technology for use in Innovative 3G/4G Base Station, Networking Infrastructure and Mobile Computing Applications, 02 August 2011 on ARM.com
  2. ↑ HiSilicon Technologies Co., Ltd. 海思半导体有限公司. ARM Holdings, abgerufen am 26. April 2013.
  3. ↑ ARM Launches Cortex-A50 Series, the World’s Most Energy-Efficient 64-bit Processors on ARM.com
  4. ↑ Richard Lai: Huawei's HiSilicon K3V3 chipset due 2H 2013, to be based on Cortex-A15. Engadget, abgerufen am 26. April 2013.
  5. ↑ Hisilicon grown into the largest local IC design companies In: Windosi, September 2012. Abgerufen im 26 April 2013 
  6. ↑ brightsideofnews.com: Huawei U9510 Ascend D Quad XL Benchmarked on ARMdevices.net
  7. ↑ Huawei introduces quad-core 10 inch tablet with 1080p display on Liliputing.com
  8. ↑ Hands On with the Huawei Ascend W1, Ascend D2, and Ascend Mate on Anandtech
  9. ↑ HiSilicon Kirin 650 SoC - Benchmarks and Specs. In: www.notebookcheck.net. Abgerufen am 4. Februar 2017 (englisch).
  10. ↑ Huawei Ascend Mate 8/Honor 7’s Kirin 940/950 Processor Performance & Specs
  11. ↑ Kirin 955, Huawei P9, P9 Plus
  12. ↑ Huawei announces the HiSilicon Kirin 960: 4xA73 + 4xA53, G71MP8, CDMA. AnandTech, 19. Oktober 2016;.
  13. ↑ Andrei Frumusanu: HiSilicon Kirin 970 - Android SoC Power & Performance Overview. In: www.anandtech.com. Abgerufen am 28. Januar 2019.
  14. ↑ Ian Cutress: Cambricon, Makers of Huawei's Kirin NPU IP, Build A Big AI Chip and PCIe Card. In: www.anandtech.com. Abgerufen am 28. Januar 2019.
  15. ↑ Klaus (12 October 2018) Hinum: ARM Mali-G76 MP10. In: Notebookcheck. Abgerufen am 3. Dezember 2018.
  16. ↑ a b c d Balong. In: www.hisilicon.com. Abgerufen am 5. Mai 2019.
  17. ↑ HiSilicon Releases Leading LTE Multi-mode Chipset | HiSilicon. In: www.hisilicon.com. Abgerufen am 5. Mai 2019.
  18. ↑ Huawei Launches the World’s First 8-Antenna 4.5G Modem Chipset. In: www.hisilicon.com. Abgerufen am 5. Mai 2019.
  19. ↑ Huawei Launches Industry-Leading 5G Multi-Mode Chipset Balong 5000 to Lead the 5G Era. In: www.hisilicon.com. Abgerufen am 5. Mai 2019.
  20. ↑ Huawei Mate 20 X 5G Teardown. In: iFixit. 25. Juli 2019, abgerufen am 27. Juli 2019 (englisch).
  21. ↑ a b c Ian Cutress: Huawei Server Efforts: Hi1620 and Arm’s Big Server Core, Ares. In: www.anandtech.com. Abgerufen am 4. Mai 2019.
  22. ↑ TaiShan 2280 Balanced Server ─ Huawei Enterprise. In: Huawei Enterprise. Abgerufen am 5. Mai 2019 (englisch).
  23. ↑ TaiShan 5280 Storage Server. In: Huawei Enterprise. Abgerufen am 5. Mai 2019 (englisch).
  24. ↑ TaiShan XA320 High-Density Server Node. In: Huawei Enterprise. Abgerufen am 5. Mai 2019 (englisch).
  25. ↑ TaiShan X6000 ARM High-Density Server. In: Huawei Enterprise. Abgerufen am 5. Mai 2019 (englisch).
  26. ↑ Huawei Unveils Industry's Highest-Performance ARM-based CPU Bringing Global Computing Power to Next Level. In: www.hisilicon.com. Abgerufen am 4. Mai 2019.
  27. ↑ TaiShan 2280 V2 Balanced Server ─ Huawei Enterprise. In: Huawei Enterprise. Abgerufen am 5. Mai 2019 (englisch).
  28. ↑ TaiShan 5280 V2 Storage Server ─ Huawei Enterprise. In: Huawei Enterprise. Abgerufen am 5. Mai 2019 (englisch).
  29. ↑ TaiShan XA320 V2 High-Density Server Node. In: Huawei Enterprise. Abgerufen am 5. Mai 2019 (englisch).
  30. ↑ a b c David Schor: Huawei Expands Kunpeng Server CPUs, Plans SMT, SVE For Next Gen. In: WikiChip Fuse. 3. Mai 2019, abgerufen am 4. Mai 2019 (amerikanisches Englisch).
  31. ↑ a b gcc.gnu.org Git - gcc.git/blob - gcc/config/aarch64/tsv110.md. In: gcc.gnu.org. Abgerufen am 13. Juni 2019.
  32. ↑ a b c Dr Ian Cutress: Hot Chips 31 Live Blogs: Huawei Da Vinci Architecture. In: www.anandtech.com. Abgerufen am 21. August 2019.
  33. ↑ Ascend | HiSilicon. In: www.hisilicon.com. Abgerufen am 4. Mai 2019.
  34. ↑ Synced: Huawei Leaps into AI; Announces Powerful Chips and ML Framework. In: Medium. 10. Oktober 2018, abgerufen am 4. Mai 2019.
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